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<h1>Debug Unit Peripheral</h1>
<null><a name="DBGU"></a><b>DBGU</b> <i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91S_DBGU">AT91S_DBGU</a>)</font></i><b>  0xFFFFF200 </b><i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91C_BASE_DBGU">AT91C_BASE_DBGU</a>)</font></i>
<table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1">Periph ID <a href="#AIC">AIC</a></font></th><th bgcolor="#FFFFCC"><font size="-1">Symbol</font></th><th bgcolor="#FFFFCC"><font size="-1">Description</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>1</b> </font></td><td><font size="-1"><i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91C_ID_SYS">AT91C_ID_SYS</a>)</font></i></font></td><td><font size="-1">System Peripheral</font></td></tr>
</null></table><br><table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1"><b>Signal</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Symbol</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>PIO controller</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b>
</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>DTXD</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA10_DTXD    ">AT91C_PA10_DTXD    </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: A Bit: 10</font></td><td><font size="-1">DBGU Debug Transmit Data</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>DRXD</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA9_DRXD    ">AT91C_PA9_DRXD    </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: A Bit: 9</font></td><td><font size="-1">DBGU Debug Receive Data</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_DBGU_CfgPMC">AT91F_DBGU_CfgPMC</a></b></font></td><td><font size="-1">Enable Peripheral clock in PMC for DBGU</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_DBGU_CfgPIO">AT91F_DBGU_CfgPIO</a></b></font></td><td><font size="-1">Configure PIO controllers to drive DBGU signals</font></td></tr>
</null></table><br><br></null><a name="DBGU"></a><h2>DBGU Software API <i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91S_DBGU">AT91S_DBGU</a>)</font></i></h2>
<a name="DBGU"></a><null><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Offset</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Field</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x0</b></font></td><td><font size="-1"><a href="AT91SAM7S256_DBGU.html#DBGU_CR">DBGU_CR</a></font></td><td><font size="-1">Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x4</b></font></td><td><font size="-1"><a href="AT91SAM7S256_DBGU.html#DBGU_MR">DBGU_MR</a></font></td><td><font size="-1">Mode Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x8</b></font></td><td><font size="-1"><a href="AT91SAM7S256_DBGU.html#DBGU_IER">DBGU_IER</a></font></td><td><font size="-1">Interrupt Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xC</b></font></td><td><font size="-1"><a href="AT91SAM7S256_DBGU.html#DBGU_IDR">DBGU_IDR</a></font></td><td><font size="-1">Interrupt Disable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x10</b></font></td><td><font size="-1"><a href="AT91SAM7S256_DBGU.html#DBGU_IMR">DBGU_IMR</a></font></td><td><font size="-1">Interrupt Mask Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x14</b></font></td><td><font size="-1"><a href="AT91SAM7S256_DBGU.html#DBGU_CSR">DBGU_CSR</a></font></td><td><font size="-1">Channel Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x18</b></font></td><td><font size="-1"><a href="AT91SAM7S256_DBGU.html#DBGU_RHR">DBGU_RHR</a></font></td><td><font size="-1">Receiver Holding Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x1C</b></font></td><td><font size="-1"><a href="AT91SAM7S256_DBGU.html#DBGU_THR">DBGU_THR</a></font></td><td><font size="-1">Transmitter Holding Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x20</b></font></td><td><font size="-1"><a href="AT91SAM7S256_DBGU.html#DBGU_BRGR">DBGU_BRGR</a></font></td><td><font size="-1">Baud Rate Generator Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x40</b></font></td><td><font size="-1"><a href="AT91SAM7S256_DBGU.html#DBGU_CIDR">DBGU_CIDR</a></font></td><td><font size="-1">Chip ID Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x44</b></font></td><td><font size="-1"><a href="AT91SAM7S256_DBGU.html#DBGU_EXID">DBGU_EXID</a></font></td><td><font size="-1">Chip ID Extension Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x48</b></font></td><td><font size="-1"><a href="AT91SAM7S256_DBGU.html#DBGU_FNTR">DBGU_FNTR</a></font></td><td><font size="-1">Force NTRST Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x100</b></font></td><td><font size="-1">DBGU_RPR (<a href="AT91SAM7S256_PDC.html#PDC_RPR">PDC_RPR</a>)</font></td><td><font size="-1">Receive Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x104</b></font></td><td><font size="-1">DBGU_RCR (<a href="AT91SAM7S256_PDC.html#PDC_RCR">PDC_RCR</a>)</font></td><td><font size="-1">Receive Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x108</b></font></td><td><font size="-1">DBGU_TPR (<a href="AT91SAM7S256_PDC.html#PDC_TPR">PDC_TPR</a>)</font></td><td><font size="-1">Transmit Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x10C</b></font></td><td><font size="-1">DBGU_TCR (<a href="AT91SAM7S256_PDC.html#PDC_TCR">PDC_TCR</a>)</font></td><td><font size="-1">Transmit Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x110</b></font></td><td><font size="-1">DBGU_RNPR (<a href="AT91SAM7S256_PDC.html#PDC_RNPR">PDC_RNPR</a>)</font></td><td><font size="-1">Receive Next Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x114</b></font></td><td><font size="-1">DBGU_RNCR (<a href="AT91SAM7S256_PDC.html#PDC_RNCR">PDC_RNCR</a>)</font></td><td><font size="-1">Receive Next Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x118</b></font></td><td><font size="-1">DBGU_TNPR (<a href="AT91SAM7S256_PDC.html#PDC_TNPR">PDC_TNPR</a>)</font></td><td><font size="-1">Transmit Next Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x11C</b></font></td><td><font size="-1">DBGU_TNCR (<a href="AT91SAM7S256_PDC.html#PDC_TNCR">PDC_TNCR</a>)</font></td><td><font size="-1">Transmit Next Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x120</b></font></td><td><font size="-1">DBGU_PTCR (<a href="AT91SAM7S256_PDC.html#PDC_PTCR">PDC_PTCR</a>)</font></td><td><font size="-1">PDC Transfer Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x124</b></font></td><td><font size="-1">DBGU_PTSR (<a href="AT91SAM7S256_PDC.html#PDC_PTSR">PDC_PTSR</a>)</font></td><td><font size="-1">PDC Transfer Status Register</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_DBGU_GetInterruptMaskStatus">AT91F_DBGU_GetInterruptMaskStatus</a></b></font></td><td><font size="-1">Return DBGU Interrupt Mask Status</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_DBGU_InterruptDisable">AT91F_DBGU_InterruptDisable</a></b></font></td><td><font size="-1">Disable DBGU Interrupt</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_DBGU_IsInterruptMasked">AT91F_DBGU_IsInterruptMasked</a></b></font></td><td><font size="-1">Test if DBGU Interrupt is Masked </font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_DBGU_InterruptEnable">AT91F_DBGU_InterruptEnable</a></b></font></td><td><font size="-1">Enable DBGU Interrupt</font></td></tr>
</null></table></null><h2>DBGU Register Description</h2>
<null><a name="DBGU_CR"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> DBGU_CR  <i>Control Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_CR">AT91C_DBGU_CR</a></i> 0xFFFFF200</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="US_RSTRX"></a><b>US_RSTRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RSTRX">AT91C_US_RSTRX</a></font></td><td><b>Reset Receiver</b><br>0 = No effect.<br>1 = The receiver logic is reset, disabling the receive function (RXDIS is set internally).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_RSTTX"></a><b>US_RSTTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RSTTX">AT91C_US_RSTTX</a></font></td><td><b>Reset Transmitter</b><br>0 = No effect.<br>1 = The transmitter logic is reset, disabling the transmit function (TXDIS and STPBRK are set internally).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_RXEN"></a><b>US_RXEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXEN">AT91C_US_RXEN</a></font></td><td><b>Receiver Enable</b><br>0 = No effect.<br>1 = The receiver is enabled if RXDIS is 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_RXDIS"></a><b>US_RXDIS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXDIS">AT91C_US_RXDIS</a></font></td><td><b>Receiver Disable</b><br>0 = No effect.<br>1 = The receiver is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_TXEN"></a><b>US_TXEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXEN">AT91C_US_TXEN</a></font></td><td><b>Transmitter Enable</b><br>0 = No effect.<br>1 = The transmitter is enabled if TXDIS is 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_TXDIS"></a><b>US_TXDIS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXDIS">AT91C_US_TXDIS</a></font></td><td><b>Transmitter Disable</b><br>0 = No effect.<br>1 = The transmitter is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="US_RSTSTA"></a><b>US_RSTSTA</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RSTSTA">AT91C_US_RSTSTA</a></font></td><td><b>Reset Status Bits</b><br>0 = No effect.<br>1 = Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR.</td></tr>
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<a name="DBGU_MR"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> DBGU_MR  <i>Mode Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_MR">AT91C_DBGU_MR</a></i> 0xFFFFF204</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">11..9</td><td align="CENTER"><a name="US_PAR"></a><b>US_PAR</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_PAR">AT91C_US_PAR</a></font></td><td><b>Parity type</b><br>When the PAR field is set to Even parity, the parity bit is set (&#147;1&#148;) if the data parity is Odd in order to ensure an even parity on the Data and Parity field.<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="US_PAR_EVEN"></a><b>US_PAR_EVEN</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_PAR_EVEN">AT91C_US_PAR_EVEN</a></font></td><td><br>Even Parity</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="US_PAR_ODD"></a><b>US_PAR_ODD</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_PAR_ODD">AT91C_US_PAR_ODD</a></font></td><td><br>Odd Parity</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="US_PAR_SPACE"></a><b>US_PAR_SPACE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_PAR_SPACE">AT91C_US_PAR_SPACE</a></font></td><td><br>Parity forced to 0 (Space)</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="US_PAR_MARK"></a><b>US_PAR_MARK</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_PAR_MARK">AT91C_US_PAR_MARK</a></font></td><td><br>Parity forced to 1 (Mark)</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="US_PAR_NONE"></a><b>US_PAR_NONE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_PAR_NONE">AT91C_US_PAR_NONE</a></font></td><td><br>No Parity</td></tr>
<tr><td align="CENTER">6</td><td align="CENTER"><a name="US_PAR_MULTI_DROP"></a><b>US_PAR_MULTI_DROP</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_PAR_MULTI_DROP">AT91C_US_PAR_MULTI_DROP</a></font></td><td><br>Multi-drop mode</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..14</td><td align="CENTER"><a name="US_CHMODE"></a><b>US_CHMODE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_CHMODE">AT91C_US_CHMODE</a></font></td><td><b>Channel Mode</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="US_CHMODE_NORMAL"></a><b>US_CHMODE_NORMAL</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_CHMODE_NORMAL">AT91C_US_CHMODE_NORMAL</a></font></td><td><br>Normal Mode: The USART channel operates as an RX/TX USART.</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="US_CHMODE_AUTO"></a><b>US_CHMODE_AUTO</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_CHMODE_AUTO">AT91C_US_CHMODE_AUTO</a></font></td><td><br>Automatic Echo: Receiver Data Input is connected to the TXD pin.</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="US_CHMODE_LOCAL"></a><b>US_CHMODE_LOCAL</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_CHMODE_LOCAL">AT91C_US_CHMODE_LOCAL</a></font></td><td><br>Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="US_CHMODE_REMOTE"></a><b>US_CHMODE_REMOTE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_US_CHMODE_REMOTE">AT91C_US_CHMODE_REMOTE</a></font></td><td><br>Remote Loopback: RXD pin is internally connected to TXD pin.</td></tr>
</null></table></font>
</td></tr>
</null></table>
<a name="DBGU_IER"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> DBGU_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_IER">AT91C_DBGU_IER</a></i> 0xFFFFF208</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="US_TXBUFE"></a><b>US_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXBUFE">AT91C_US_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="US_RXBUFF"></a><b>US_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXBUFF">AT91C_US_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">30</td><td align="CENTER"><a name="US_COMM_TX"></a><b>US_COMM_TX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_COMM_TX">AT91C_US_COMM_TX</a></font></td><td><b>COMM_TX Interrupt</b><br>0 = COMM_TX is at 0.<br>1 = COMM_TX is at 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31</td><td align="CENTER"><a name="US_COMM_RX"></a><b>US_COMM_RX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_COMM_RX">AT91C_US_COMM_RX</a></font></td><td><b>COMM_RX Interrupt</b><br>0 = COMM_RX is at 0.<br>1 = COMM_RX is at 1.</td></tr>
</null></table>
<a name="DBGU_IDR"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> DBGU_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_IDR">AT91C_DBGU_IDR</a></i> 0xFFFFF20C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="US_TXBUFE"></a><b>US_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXBUFE">AT91C_US_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="US_RXBUFF"></a><b>US_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXBUFF">AT91C_US_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">30</td><td align="CENTER"><a name="US_COMM_TX"></a><b>US_COMM_TX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_COMM_TX">AT91C_US_COMM_TX</a></font></td><td><b>COMM_TX Interrupt</b><br>0 = COMM_TX is at 0.<br>1 = COMM_TX is at 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31</td><td align="CENTER"><a name="US_COMM_RX"></a><b>US_COMM_RX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_COMM_RX">AT91C_US_COMM_RX</a></font></td><td><b>COMM_RX Interrupt</b><br>0 = COMM_RX is at 0.<br>1 = COMM_RX is at 1.</td></tr>
</null></table>
<a name="DBGU_IMR"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> DBGU_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_IMR">AT91C_DBGU_IMR</a></i> 0xFFFFF210</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="US_TXBUFE"></a><b>US_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXBUFE">AT91C_US_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="US_RXBUFF"></a><b>US_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXBUFF">AT91C_US_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">30</td><td align="CENTER"><a name="US_COMM_TX"></a><b>US_COMM_TX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_COMM_TX">AT91C_US_COMM_TX</a></font></td><td><b>COMM_TX Interrupt</b><br>0 = COMM_TX is at 0.<br>1 = COMM_TX is at 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31</td><td align="CENTER"><a name="US_COMM_RX"></a><b>US_COMM_RX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_COMM_RX">AT91C_US_COMM_RX</a></font></td><td><b>COMM_RX Interrupt</b><br>0 = COMM_RX is at 0.<br>1 = COMM_RX is at 1.</td></tr>
</null></table>
<a name="DBGU_CSR"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> DBGU_CSR  <i>Channel Status Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_CSR">AT91C_DBGU_CSR</a></i> 0xFFFFF214</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="US_TXBUFE"></a><b>US_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_TXBUFE">AT91C_US_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="US_RXBUFF"></a><b>US_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_RXBUFF">AT91C_US_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">30</td><td align="CENTER"><a name="US_COMM_TX"></a><b>US_COMM_TX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_COMM_TX">AT91C_US_COMM_TX</a></font></td><td><b>COMM_TX Interrupt</b><br>0 = COMM_TX is at 0.<br>1 = COMM_TX is at 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31</td><td align="CENTER"><a name="US_COMM_RX"></a><b>US_COMM_RX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_COMM_RX">AT91C_US_COMM_RX</a></font></td><td><b>COMM_RX Interrupt</b><br>0 = COMM_RX is at 0.<br>1 = COMM_RX is at 1.</td></tr>
</null></table>
<a name="DBGU_RHR"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> DBGU_RHR  <i>Receiver Holding Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_RHR">AT91C_DBGU_RHR</a></i> 0xFFFFF218</font></null></ul><br>Last character received if RXRDY is set. When number of data bits is less than 8 bits, the bits are right-aligned. All non-sig-nificant bits read zero.<a name="DBGU_THR"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> DBGU_THR  <i>Transmitter Holding Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_THR">AT91C_DBGU_THR</a></i> 0xFFFFF21C</font></null></ul><br>Next character to be transmitted after the current character if TXRDY is not set. When number of data bits is less than 8 bits, the bits are right-aligned.<a name="DBGU_BRGR"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> DBGU_BRGR  <i>Baud Rate Generator Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_BRGR">AT91C_DBGU_BRGR</a></i> 0xFFFFF220</font></null></ul><br>Clock Divisor:<br>0 Disables Clock<br>1 Clock Divisor Bypass<br>2 to 65535 Baud Rate = Selected Clock / (CDx16)<a name="DBGU_CIDR"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> DBGU_CIDR  <i>Chip ID Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_CIDR">AT91C_DBGU_CIDR</a></i> 0xFFFFF240</font></null></ul><br>Hard-coded value. Must be specified before debug unit synthesis.<a name="DBGU_EXID"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> DBGU_EXID  <i>Chip ID Extension Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_EXID">AT91C_DBGU_EXID</a></i> 0xFFFFF244</font></null></ul><br>Hard-coded value. Must be specified before debug unit synthesis.<a name="DBGU_FNTR"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> DBGU_FNTR  <i>Force NTRST Register</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="AT91SAM7S256_h.html#AT91C_DBGU_FNTR">AT91C_DBGU_FNTR</a></i> 0xFFFFF248</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_FORCE_NTRST"></a><b>US_FORCE_NTRST</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_US_FORCE_NTRST">AT91C_US_FORCE_NTRST</a></font></td><td><b>Force NTRST in JTAG</b><br>0 = NTRST is not forced.<br>1 = NTRST is forced.</td></tr>
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<a name="DBGU_PDC"></a><h4><a href="#DBGU">DBGU</a>: <i><a href="AT91SAM7S256_h.html#AT91S_PDC">AT91S_PDC</a></i> DBGU_PDC  <i>PDC interface</i></h4><ul><null><font size="-2"><li><b>DBGU</b> <i><a href="#AT91C_DBGU_DBGU">AT91C_DBGU_DBGU</a></i> 0xFFFFF300</font></null></ul></null><hr></html>
